The biggest challenge in designing step-up DC-DC converters relates to the ratio between output voltage and input voltage. The complexity of a DC-DC converter is inversely proportional to Vin/Iin. There is an even bigger problem when power in the range of 2-4 kW and higher with input voltage in the range of 10-12 VDC are required. As depicted in FIG. 15, when the ratio between input voltage and input current (Vin/Iin) is above 1, the problem will be smaller. i.e. The higher the number, the smaller the problem.
When the ratio is below 1, the problem increases as the ratio drops. For example, 10 VDC and 1000 ADC is problematic. The requirement for DC-DC isolation conversion with power in the range of 20-30 kW for automotive application is not rare. A common requirement is 24 VDC to 400 VDC and 48 VDC to 400 VDC. In this case, engineers typically connect a number of power stages in parallel. This works somewhat, but it has a big disadvantage: there are too many active switches and transformers, which require complex control, higher costs, and reduced reliability.
One key advantage of the present invention is reduction in complexity of the power transformer. The voltage across the low voltage side of transformer is, on average, twice higher than the input voltage, so the current via the low voltage side of the transformer will have an average value of half of the input current. This results in a reduction in the turns ratio of the transformer and as a result the design and the construction of the transformer will be easier, the efficiency of the transformer will increase, and the cost will be reduced. Additional objects and advantages are achieved because the topology of the present invention does not require a big block capacitor and has a relatively small ripple current on low voltage side—because of input inductors.
FIG. 1 depicts one embodiment of the present invention. FIGS. 1A & 1B depict a schematic diagram of a simplified/representative view of FIG. 1, used in some cases for ease of discussion. The regulation of output voltage is accomplished by changing the duty cycle of switches S1 and S3. The switching of S2 and S4 is complementary to the switching of S1 and S3 (i.e. S1 & S4 open when S2 & S3 closed, and vice versa).
The power stage has 3 modes of operation: Duty cycle of 50% wherein “on” time of S1 and S3 is half of commutation frequency, duty cycle of less than 50% wherein “on” time is less than half of the commutation frequency, and duty cycle of greater than 50% wherein “on” time is more than half of the commutation frequency. The selection of a mode will be determined by how much gain is required. In other words, the ratio between input and output voltage. Capacitors C1 and C2 will charge to an average voltage following this formula.
In one preferred embodiment, capacitors C1 and C2 are big enough so that we can ignore the ripple voltage, inductors L1 and L2 are big enough so that we can ignore ripple current, and the resonant frequency of resonant circuit Lr and Cr is equal to the commutation frequency.
FIGS. 5A-6B show operational characteristics for a 50% duty cycle. Starting at time t0, Capacitors C1 and C2 are charged with a polarity as shown in FIG. 5B. At time t0 S1 is turned-on and current from source V1 flows via inductor L1 and S1. At the same time (t0) S4 is turned-on and completes a circuit to discharge C1 via the resonant circuit Lr and Cr through the load. The current in this circuit starts from zero, will be sinusoidal in waveform, and reaches zero at time t1. At the same time S4 completes a circuit to charge C2 through inductor L2, since S3 is turned-off this time. The switch S4 has to be bidirectional because current flows through it in both directions. The current via S4 starts equal with the current in inductor L2 and decays because the current from capacitor C1 is in the opposite direction, and when current in capacitor C1 reaches maximum the current via switch S4 will have reversed direction. When the current in C1 reaches zero (time t1) the current via S4 will be the same as at time t0. At time t1 S1 and S4 are turned-off, S3 and S2 are turned-on, and new half cycle (t1-t2) starts, similar to period t041, but the current flowing via resonant circuit will be in the opposite direction to that during the period t041.
FIGS. 7A-10B show operational characteristics for an approximately 40% duty cycle. Starting at time t0, switch S4 is ON. The current via S1 begins with the same value as the current in L1, and discharges capacitor C1 via resonant circuit. The current via S4 at time t0 is equal to the current via L2 and will be reduced by the current from C1 because it flows in the opposite direction to the current from L2. At time t1 S1 is turned-off, interrupting the current which will be the summary of the current in L1 and the current flowing through C1 and resonant circuit. Also at time t1, S2 turns on and current flows via S2 matching the current which was interrupted by S1. The current via resonant circuit at t1 starts to decay and at time t2 it will be zero. Between t2 and t3 currents flow via S2 and S4 and matching the currents via L1 and L2. At time t3, S3 turns on and S4 turns off beginning a new conduction period (t3-t4), similar to time period t0-t3.
FIGS. 11A-14B show operational characteristics for an approximately 60% duty cycle. Starting at time t0, S1 is staying “on” conducting current via inductor L1. Also at time t0, S3 turns-off and S4 turns-on. This commutation completes a circuit to discharge C1 via resonant circuit. This current is starting from zero and rising sinusoidally. At time t1 switch S4 turns-off and S3 turns-on. This commutation event provides a path for current to flow via resonant circuit to C2 and S3. So, switch S3 carries the summary of two currents, one from L2 and another one from resonant circuit, but they are in opposite directions. The current via resonant circuit will linearly decay, and at time t2 it reaches zero. In time period t2-t3, current will flow only via S1 and S3, and will be equal to the currents in L1 and L2, respectively. At time t3, switch S1 turns-off and S2 turns-on and a new period begins (t3-t4), similar to period t0-t3.
Other configurations may be used with resonant capacitors. In one embodiment, capacitors C1 and C2 are the resonant Capacitors, Switches S1 and S3 turn-off purely ZVS (Zero Voltage Switched) under full load. When capacitors C1 and C2 are of small value, the resonant capacitance will be determined by the combination of capacitors C1, C2 and the capacitor which is connected in series with resonant inductor Lr. In this case, the ripple voltage on capacitors C1 and C2 can be high under full load.
When capacitors C1 and C2 are the resonant capacitors, the ripple voltage on C1 and C2 can reach 100% under full load conditions and switches S1 and S4 will turn-off under purely ZVS. It should be noted that in practical implementation, switches S1 and S3 turn-on under ZCS (Zero Current Switched) conditions, because practically there will always be a small inductor which is connected in series with capacitors C1 and C2. All this helps to significantly reduce switching losses. This topology has many varieties of behavior which depend on value of capacitors C1 and C2. It should also be noted that RMS current via these capacitors is almost equal to RMS current via the primary transformer winding. The foregoing considerations necessitate that attention should be paid to the selection of value and type of these capacitors.
FIGS. 17A through 17C depict 50%, 40%, 60% duty cycles, respectively, wherein Ch1=gate S1, Ch2=S1, Ch3=S2, & Ch4=current via low voltage side of transformer; 80 A/div. The following table shows the measured results.
TABLEmeasured results (FIGS. 17A through 17C)VinVoutPout WEff  10.517016000.9351517021000.94 2238031000.9452738031000.9443038031000.9415238011000 0.94 6038010000 0.9458038011000 0.94 
FIG. 2 depicts a DC-AC converter without a DC-link. The following table shows the practical results from this DC-AC converter. In this case the converter can operate as a bidirectional converter and operate as a charger.
TABLE(DC-AC converter of FIG. 2)VinVoutPoutWEff1112010000.9211212012000.9271412012000.931
In this case, the converter can operate as a bidirectional converter. For step-up DC-DC isolation converters with input voltage below 100 VDC, it is reasonable to use paralleling when the input current is over 600-700 A. The cost of paralleling below this current will be at least twice as high as a single stage under the same conditions (Vin, Pout, efficiency, and commutation frequency).
The following tables show comparisons of real implementations of these topologies. The cost of the proposed topology is smaller than that of others and it has a wider application area. The proposed topology has better results as far as cost and application area by Vin, but it is limited by capacitors C1 and C2. In other words, more attention should be paid to the selection of these parts. Power transformer characteristics are improved by reduction of turn ratio. Additionally, it is very reasonable to use this topology for DC-AC converter without DC-link, when input ripple current is not desired. The paralleling input power stages have minimum twice higher cost and are not competitive. In other words, the proposed topology is a better solution for higher power at low voltage than parallel input stages.
The technical aspects and cost characteristics of the proposed topology (FIG. 1) is compared to the topologies depicted in FIGS. 3 & 4. The comparison of cost per kW was made according to the following norms: Vin, Vout, Pout and efficiency are the same for each topology. The following table shows a comparison of the proposed topology of the present invention (“Prop”) vs N1 (FIG. 3), N2 (FIG. 4), & DAB (Double Active Bridge). The latter having received a lot of attention.
TABLEBlockCostMaxVinVoutCommLimit bySwIndC1 kWDAB150 A10-1000-1000 50 kHzTurn-off8noHuge1.3-1.5N1200 A30-1000-1000100 kHzTurn-off42no1.2-1.4N2600 A10-40Vmax/Vmin = 2300 kHzX-form6no11.1-1.2Prop600 A10-1000-1000200 kHzC1 & C242no1.0
The following table shows comparisons of implementations of the aforementioned topologies. As can be seen, the cost of the proposed topology is lower than that of others and it has a wider application area. Also, it is very reasonable to use this topology for a DC-AC converter without a DC-link, when low input ripple current is desired. Finally, the proposed topology is a better solution for higher power at low voltage than parallel input stages.
TABLEPoutVinVoutCommEffDAB1.7 kW10-14360 20 kHz92.0DAB2.4 kW30750 40 kHz94.5N11.0 kW20-50350 50 kHz95.8N11.4 kW12300 20 kHz92.0N11.6 kW12300 20 kHz88.0N23.5 kW10.5-16  360150 kHz93.5N27.5 kW20-30600120 kHz94.0Prop1.7 kW10.5-15  170120 kHz93.5Prop3.1 kW22-30380120 kHz94.5Prop7.0 kW42-72380100 kHz96.5
Table
Examples of component values for different resonance configurations for a sample converter with 12V input, 360V output at 2.8 kW:
Primary sideSecondary sideCombined ComponentresonanceresonanceResonanceC1/C210uF400uF24uFC3/C510uF0.1uF0.1uFL36.5uH6uH8.5uH